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? semiconductor component s industries, llc, 2017 1 publication order number : june 2017 - rev. 2 lc72722pm/d www.onsemi.com ordering information see detailed ordering and shipping info rmation on page 18 of this data sheet. * computer control bus (ccb) is an on semiconductor?s original bus format and the bus addresses are controlled by on semiconductor. lc72722pm rds / rbds single-chip signal processor overview the lc72722pm is a single-chip syst em ic that implement the signal processing required by the european broadcasting union rds (radio data system) standard and by the us nrsc (national radio system committee) rbds (radio broadcast da ta system) standard. this ic include band-pass filter, demodulator, synchronization, and error correction circuits as well as data buffer ra m on chip and perf orm effective error correction using a soft-decision error correction technique. functions ? band-pass filter : switched capacitor filter (scf) ? demodulator : rds data clock regeneration and demodulated data reliability information ? synchronization : block synchronization detection (with variable backward and forward protection conditions) ? error correction : soft-decision/ hard-decision error correction ? buffer ram : adequate for 24 blocks of data (about 500 ms) and flag memory ? data i/o : ccb* interface (power on reset) features ? error correction capability improved by soft-decision error correction ? the load on the control micropro cessor can be reduced by storing decoded data in the on-chip data buffer ram. ? two synchronization detection circuits provide continuous and stable detection of the synchronization. ? data can be read out starting with the backward-protection block data after a synchronization reset. ? fully adjustment free specifications ? operating power-supply voltage : 4.5 to 5.5 v ? operating temperature : ? 40 to +85 ? c ? package : mfp24 (375 mil) soic24 w / mfp24 (375 mil)
lc72722pm www.onsemi.com 2 specifications absolute maximum ratings at ta = 25 ? c, vssd = vssa = 0 v parameter symbol pin name ratings unit maximum supply voltage vddmax vddd, vdda ? 0.3 to +7.0 v maximum input voltage vin1max cl, di, ce, syr, t1, t2, t3, t4, t5, t6, t7, sync ? 0.3 to +7.0 v vin2max xin ? 0.3 to vddd+0.3 v vin3max mpxin, cin ? 0.3 to vdda+0.3 v maximum output voltage vo1max do, sync, rds-id, t3, t4, t5, t6, t7 ? 0.3 to +7.0 v vo2max xout ? 0.3 to vddd+0.3 v vo3max flout ? 0.3 to vdda+0.3 v maximum output current io1max do, t3, t4, t5, t6, t7 +6.0 ma io2max xout, flout +3.0 ma io3max sync, rds-id +20.0 ma allowable power dissipation pdmax (ta ?? 85 ? c) 175 mw operating temperature topr ? 40 to +85 ? c storage temperature tstg ? 55 to +125 ? c allowable operating ranges at ta = ? 40 to 85 ? c, vssd = vssa = 0 v parameter symbol pin name conditions ratings unit min typ max supply voltage vdd1 vddd, vdda 4.5 5.0 5.5 v vdd2 vddd serial data hold voltage 2.0 v input high-level voltage v ih cl, di, ce, syr, t1, t2 0.7vddd 6.5 v input low-level voltage v il cl, di, ce, syr, t1, t2 0 0.3vddd v output voltage v o do, sync, rds-id, t3, t4, t5, t6, t7 6.5 v input amplitude v in1 mpxin f = 57 ? 2 khz 50 mvrms v in2 100% modulation composite 100 mvrms v xin xin 400 1500 mvrms guaranteed crystal oscillator frequencies xtal xin, xout ci ?? 120 ? (xs = 0) 4.332 mhz ci ?? 70 ? (xs = 1) 8.664 mhz crystal oscillator frequency deviation txtal xin, xout fo = 4.332 mhz, 8.664 mhz ? 100 ppm data setup time tsu di, cl 0.75 ? s data hold time thd di, cl 0.75 ? s clock low level time tcl cl 0.75 ? s clock high level time tch cl 0.75 ? s ce wait time tel ce, cl 0.75 ? s ce setup time tes ce, cl 0.75 ? s ce hold time teh ce, cl 0.75 ? s ce high-level time tce ce 20 ms data latch change time tlc 1.15 ? s data output time tdc do,cl differs depending on the value of the pull-up resistor used. 0.46 ? s tdh do,ce 0.46 ? s stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc72722pm www.onsemi.com 3 electrical characteristics at ta = ? 40 to 85 ? c, vssd = vssa = 0 v parameter symbol pin name conditions ratings unit min typ max input resistance r mpxin mpxin-vssa f = 57 khz 43.0 k ? rcin c in -vssa f = 57 khz 100.0 k ? internal feedback resistance rf xin 1.0 m ? center frequency fc flout 56.5 57.0 57.5 khz ? 3 db band width bw -3db flout 2.5 3.0 3.5 khz gain gain mpxin-flout f = 57 khz 28 31 34 db stop band attenuation att1 flout ? f = ? 7 khz 30 db att2 flout f < 45 khz, f > 70 khz 40 db att3 flout f < 20 khz 50 db reference voltage output vref vref vdda = 5.0 v 2.5 v hysteresis v his cl, di, ce, syr, t1, t2 0.1vddd v output low-level voltage v ol1 do, t3, t4, t5, t6, t7 i = 2 ma 0.5 v v ol2 sync, rds-id i = 8 ma 0.5 v input high-level current i i ih1 cl, di, ce, syr, t1, t2 v i = vddd 5.0 ? a i i ih2 xin v i = vddd 2.0 11.0 ? a input low-level current i i il1 cl, di, ce, syr, t1, t2 v i = 0 v 5.0 ? a i i il2 xin v i = 0 v 2.0 11.0 ? a output off leakage current i i off do, sync, rds-id, t3, t4, t5, t6, t7 v o = 6.5 v 5.0 ? a current drain idd vddd, vdda 9 ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc72722pm www.onsemi.com 4 package dimensions unit : mm soic24 w / mfp24 (375 mil) case 751cf issue a soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. (unit: mm) 9.75 0.52 1.15 1.27 xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. xxxxxxxxxx ymddd to
lc72722pm www.onsemi.com 5 pin assignment block diagram vref mpxin vdda vssa flout cin t1 t2 t3 (rdcl) t4 (rdda) t5 (rsft) xout lc72722pm top view 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 syr ce di cl do rds-id sync t7 (correc/ari-id/ta/beo) t6 (error/57k/tp/be1) vssd vddd xin vdda vssa mpxin reference voltage antialiasing filter vref 57khz bpf (scf) smoothing filter - + flout cin vref pll (57khz) clock recovery (1187.5hz) data decoder vddd +5.0v vssd rds-id sync/ec controller sync syr ccb test do cl di ce t1 t2 t3 to t7 ram (24 block data) error correction (soft decision) memory control osc/divider clk (4.332mhz) xin xout sync detect-1 sync detect-2 +5.0v
lc72722pm www.onsemi.com 6 pin functions pin no. pin name function i/o pin circuit 1 vref reference voltage output (vdda/2) output 2 mpxin baseband (multiplexed) signal input input 5 flout subcarrier output (filter output) output 7 cin subcarrier input (comparator input) input 3 vdda analog system power supply (+5v) ?? ? 4 vssa analog system ground ? ? 12 xout crystal oscillator output (4.332/8.664mhz) output 13 xin crystal oscillator input (external reference signal input) input 7 t1 test input (this pin must always be connected to ground.) 8 t2 test input (standby control) 0:normal operation, 1:standby state (crystal oscillator stopped) 9 t3(rdcl) test i/o (rds clock output) i/o * 10 t4(rdda) test i/o (rds data output) 11 t5(rsft) test i/o (soft-de cision control data output) 16 t6 (error/57k/be1) test i/o (error status, regenerated carrier, error block count) 17 t7 (correc/ari-id/be0) test i/o (error correction status, sk detection, error block count) 18 sync block synchronization detection output 19 rds-id rds detection output output 20 do data output 21 cl clock input data input chip enable input 22 di 23 ce 24 syr synchronization and ram address reset (active high) 14 vddd digital system power supply (+5v) ?? ? 15 vssd digital system ground ? ? note : * normally function as an output pin. used as an i/o pin in test mode, which is not available to user applications. serial data interface (ccb) vdda vdda vdda vddd v ref vssa vssa vssd vssa x out x in vssd vssd s vssd s vssd
lc72722pm www.onsemi.com 7 ccb output data format 1. each block of output data consists of 32 bits (4 bytes), of which 2 bytes are rds data and 2 bytes are flag data. 2. any number of 32-bits output data blocks can be output consecutively. 3. when there is no data that can be read out in the in ternal memory, the system outputs blocks of all-zero data consecutively. 4. if data readout is interrupted, the next read operation star ts with the 32-bit data block whose readout was interrupted. however, if only the last bit is remaining to be read, it will not be possible to re-read that whole block. 5. the check bits (10 bits) are not output. 6. the data valid (owd) must not be referred to. 7. when the first leading bits are not ?1010?, the read in data is in invalid, and read operation is cancelled. (1) offset word detection flag (1bit) : owd owd offset word detection 1 detected 0 not detected (protection function operating) (2) offset word information flag (3bit) : b0 to b2 b 2 b 1 b 0 offset word 0 0 0 a 0 0 1 b 0 1 0 c 0 1 1 c? 1 0 0 d 1 0 1 e 1 1 0 unused 1 1 1 unused di do b 0 0 1010 o w d r f 1 r f 0 a r i s y c d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 b 2 e 2 e 1 e 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 b 1 b 0 r e 0110110 b 1 b 2 b 3 a 0 a 1 a 2 a 3 ccb address 6c output data / first bit last bit (8) rds data (7) error information flags (6) synchronization established flag (5) ari(sk) detection flag (4) ram data remaining flags (3) consecutive ram read out possible flag (2) offset word information flags (1) offset word detection flag fixed pattern (1010)
lc72722pm www.onsemi.com 8 (3) consecutive ram read out possible flag (1bit) : re re ram data information 1 the next data to be read out is in ram 0 this data item is the last item in ram, ant the next data is not present. (4) ram data remaining flag (2bits) : rf0,rf1 rf1 rf0 remaining data in ram (number of blocks) 0 0 1 to 7 0 1 8 to 15 1 0 16 to 23 1 1 24 caution : this value is only meaningful wh en re is 1. when re is 0, there is no data in ram, even if rf is 00. if a synchronization reset was applied using syr, then the backward protection block data that was written to memory is also counted in this value. (5) ari(sk) detection flag (1bit) : ari ari sk signal 1 detected 0 not detected (6) synchronization established flag (1bit) : syc syc synchronization detection 1 synchronized 0 not synchronized caution : this flag indicates the synchronization state of the circuit at the point when the data block being output was receiv ed. on the other hand, the sync pin (pin18) output indica tes the current synchronization state of the circuit. (7) error information flags (3bits) : e0 to e2 e 2 e 1 e 0 number of bits corrected 0 0 0 0 (no errors) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 correction not possible 1 1 1 unused caution : if the number of errors exceeds the value of the ec 0 to ec2 setting (see the section on the ccb input format), the error information flags will be set to the ?correction not possible? value. (8) rds data (16bits) : d0 to d15 this data is output with the msb first ant the lsb last. caution : when error correction was not possibl e, the input data is output without change.
lc72722pm www.onsemi.com 9 ccb input data format (1) synchronization protection (forward protection) method setting (4bits) : fs0 to fs3 fs3 = 0 : if offset words in the correct order could not be detected continuously during the number of blocks specified by fs0 to fs2, take that to be a lost synchronization sate. fs3 = 1 : if blocks with uncorrectable errors were received consecutively during the number of blocks specified by fs0 to fs2, take that to be a lost synchronization state. f s 0 f s 1 f s 2 condition for detecting lost synchronization 0 0 0 if 3 consecutive blocks matching the fs3 condition are received. 1 0 0 if 4 consecutive blocks matching the fs3 condition are received. 0 1 0 if 5 consecutive blocks matching the fs3 condition are received. 1 1 0 if 6 consecutive blocks matching the fs3 condition are received. 0 0 1 if 8 consecutive blocks matching the fs3 condition are received. 1 0 1 if 10 consecutive blocks matching the fs3 condition are received. 0 1 1 if 12 consecutive blocks matching the fs3 condition are received. 1 1 1 if 16 consecutive blocks matching the fs3 condition are received. initial value : fs0 = 0, fs1 = 1, fs2 = 0, fs3 = 0 (2) synchronization detectio n method setting (1bit) : bs bs synchronization detection conditions 0 if during 3 blocks, 2 blocks of offset words were detected in the correct order. 1 if the offset words were detected in the correct order in 2 consecutive blocks. initial value : bs = 0 di b 0 0 b 1 1 b 2 0 b 3 1 a 0 0 a 1 1 a 2 1 a 3 0 [1] ccb address 6a f s 0 f s 1 f s 2 f s 3 b s s y r o w e e c 0 e c 1 e c 2 e c 3 e c 4 c t 0 (12) circuit control (5) error correction method setting (4) ram write control (3) synchronization and ram address reset (2) synchronization detection method setting (1) synchronization protection method setting in1 data, first bit di b 0 1 b 1 1 b 2 0 b 3 1 a 0 0 a 1 1 a 2 1 a 3 0 [2] ccb address 6b c t 1 s p 0 s p 1 x s p l 0 p l 1 p t 0 p t 1 p t 2 t s 0 t s 1 t s 2 (11) test mode settings (10) output pin settings (9) rds/rbds selection (8) demodulation circuit phase control (7) crystal oscillator frequency selection (12) circuit control in2 data, first bit r m t s 3 caution : the bits labeled with an asterisk must be set to 0. (6) intermittent do output setting
lc72722pm www.onsemi.com 10 (3) synchronization and ram address reset (1bit) : syr syr synchronization detection circuit ram 0 normal operation (reset cleared) normal wr ite (see the description of the owe bit) 1 forced to the unsynchronized state (synchronization reset) after the reset is cleared, start writing from the data prior to the establishment of synchronization, i.e. the data in b ackward protection. initial value : syr = 0 caution : 1. to apply a synchronization reset, set syr to 1 temporar ily using ccb, and then set it back to 0 again using ccb. the circuit will start synchronization capt ure operation at the point syr is set to 0. 2. the syr pin (pin24) also provides an identical reset control operation. applic ations can use either method. however, the control method that is not used must be set to 0 at all times. any pulse with a width of over 250 ns will suffice. 3. a reset must be applied immediately after the reception channel is changed. if a reset is not applied, recept ion data from the previous channe l may remain in on-chip memory. 4. data read out after a synchronization reset is read out starting with the back ward protection block data preceding the establishment of synchronization. (4) ram write control (1bit) : owe owe ram write conditions 0 only data for which synchronization had been established is written. 1 data for which synchronization not has been established (unsynchronized data) is also written. (however, this applies when syr = 0.) initial value : owe = 0 (5) error correction method setting (5bits) : ec0 to ec4 initial values : ec0 = 0, ec1 = 1, ec2 = 0, ec3 = 0, ec4 = 1 caution : 1. if soft-decision a or soft-decision b is specified, so ft-decision control will be pe rformed even if the number of bits corrected is set to 0 (error detection only). with th ese settings, data will be out put for blocks with no errors. 2. as opposed to soft-decision b, the soft-decision a setting suppresses soft decision error correction. (6) intermittent do output setting sp0 sp1 do output state 0 0 do goes low when one or more blocks of data are written to memory. 1 0 do goes low when 4 or more blocks of data are written to memory. 0 1 do goes low when 8 or more blocks of data are written to memory. 1 1 do goes low when 12 or more blocks of data are written to memory. initial values : sp0 = 0, sp1 = 0 e c 0 e c 1 e c 2 number of bits corrected 0 0 0 0 (error detection only) 1 0 0 1 or fewer bits 0 1 0 2 or fewer bits 1 1 0 3 or fewer bits 0 0 1 4 or fewer bits 1 0 1 5 or fewer bits 0 1 1 illegal value 1 1 1 illegal value e c 3 e c 4 soft-decision setting 0 0 mode0 hard decision 1 0 mode1 soft decision a 0 1 mode2 soft decision b 1 1 illegal value
lc72722pm www.onsemi.com 11 (7) crystal oscillator frequen cy selection (1bit) : xs xs = 0 : 4.332mhz (initial value : xs = 0) xs = 1 : 8.664mhz (8) demodulation circuit phase control (2bits) : pl0, pl1 pl0 pl1 demodulation circuit phase control 0 0/1 ? normal operation ? when ari presence or absence is unclear. 1 0 if the circuit determines that the ari signal is absent : 90 ? phase 1 if the circuit determines that the ari signal is present : 0 ? phase initial values : pl0 = 0, pl1 = 1 caution : 1. when pl0 is 0 (normal operation), the ic detects th e presence or absence of the ari signal and reproduces the rds data by automatically controlling the demodul ation phase with respect to the reproduced carrier. however, the initial phase following a synchronization reset is set by pl1. 2. if pl0 is set to 1, the demodulation circuit phase is locked according to the pl1 setting at either 90 ? (pl1 = 0) or 0 ? (pl1 = 1), allowing rds data to be reproduced. when ar i is not present, pl1 should be set to 0, since the rds data is reproduced by detecting at a phase of 90 ? with respect to the reproduced carrier. when ari is present, pl1 should be set to 1, since detection is at 0 ? . in cases where the ari presence is known in advance, more stable reproduction can be achieved by fixing th e demodulation phase in this manner. (9) rds/rbds(mmbs) selection (1bit) : rm rm rbds decoding method 0 none only rds data is decoded correctly (offset word e is not detected.) 1 provided rds and mmbs data is decoded correctly (offset word e is also detected.) initial value : rm=0 (10) output pin settings (3bits) : pt0 to pt2 these bits control the t3, t4, t5, t6, t7, sync, and rds-id pins mode p t 0 p t 1 p t 2 t3 t4 t5 t6 t7 rdcl rdda rsft error 57k tp be1 correc ari-id ta be0 0 0 0 0 ?? ?? ?? ?? ?? ? ?? ?? ?? ?? ?? 1 1 0 0 ? ? ?? ?? ?? ?? ? ?? ?? ?? ? ? ?? 2 0 1 0 ? ? ? ? ? ? ?? ? ? ??? ?? ? ? ?? ?? 3 1 1 0 ? ? ? ? ? ? ? ? ?? ? ?? ? ? ?? ?? ?? 4 0 0 1 ?? ?? ?? ?? ?? ?? ? ?? ?? ? ? ? ? 5 1 0 1 ? ? ? ? ? ? ?? ?? ? ? ?? ?? ?? ? ? ?? 6 0 1 1 ? ? ? ? ? ? ?? ? ? ??? ?? ? ? ?? ?? 7 1 1 1 ? ? ? ? ? ? ? ? ?? ? ?? ? ? ?? ?? ?? ? : open, ? , ? : output enabled ( ? = reverse polarity) initial value : pt0 = 1, pt1 = 1, pt2 = 0 (mode 3) caution : 1. when pt2 is set to 1, the polarity of th e t6(error/57k/tp), t7(correc/ari-id/ta), sync, and rds-id pins changes to active high. 2. the output pins (t3 to t7, sync, and rds-id) are all open-drain pins, a nd require external pull-up resistors to output data. mode1 (pt2 = 0) pin t6 (tp) tp = 0 detected high (1) tp = 1 detected low (0) tp = traffic program code
lc72722pm www.onsemi.com 12 mode1 (pt2 = 0) pin t7 (ta) ta = 0 detected high (1) ta = 1 detected low (0) ta = traffic announcement code mode2 (pt2 = 0) pin t7 (ari-id) no sk high (1) sk present low (0) mode3 (pt2 = 0) pin t6 (error) pin t7 (correc) correction not possible low (0) low (0) errors corrected high (1) low (0) no errors high (1) high (1) mode = 4 pin t6 (be1) pin t7 (be0) number of error blocks (b) b=0 low (0) low (0) 1 ? b ? 20 low (0) high (1) 20 ? b ? 40 high (1) low (0) 40 ? b ? 48 high (1) high (1) these pins indicate the number of blocks in a set of 48 blocks that had errors before correction. the output polarity of these pins is fi xed at the values listed in the table. mode (pt2 = 0) the sync pin 0 to 2 when synchronized : low (0), when unsynchronized: high (1) 3 when synchronized : goes high for a fixed period (421 ?
lc72722pm www.onsemi.com 13 rdcl / rdda / rsft and error / correc / sync output timing (1) timing 1 note : when pt2 = 0, rdda and rsft must be acquired on the falling edge of rdcl. (2) timing 2 (mode 3, pt2 = 0) input data error crrection sync output error output correc output sync ng sync ok tp1 tp1 sync ok sync ok sync ok sync ok sync ng sync ng data corrected no errors no errors data corrected uncorrectable uncorrectable 17 s 421 s 421 s tp2 tp1 17 s rdcl output rsft output rdda output
lc72722pm www.onsemi.com 14 serial data input and output methods data is input and output using the ccb (computer contro l bus), which is our audio ic serial bus format. this ic adopts an 8-bit address ccb format. i/o mode (lsb) address (msb) comment b0 b1 b2 b3 a0 a1 a2 a3 [1] in1 (6a) 0 1 0 1 0 1 1 0 ? control data input mode, also referred to as ? serial data input ? mode. ? 16bit data input mode [2] in2 (6b) 1 1 0 1 0 1 1 0 [3] out (6c) 0 0 1 1 0 1 1 0 ? data output mode ? the data for multiple blocks can be output sequentially in this mode. ce cl di do b0 b1 b2 b3 a0 a1 a2 a3 first data in1/2 first data out first data out 1 1 2 1 2 2 i/o mode determined for the cl normal high state for the cl normal low state
lc72722pm www.onsemi.com 15 (1) serial data input (in1 / in2) t su , t hd , t el , t es , t eh ? 0.75 ? s t lc ? 1.15 ? s t ce ? 20 ms ? cl : normal high ? cl : normal low (2) serial data output (out) t su , t hd , t el , t es , t eh ? 0.75 ? s t dc , t dh ? 0.46 ? s t ce ? 20 ms ? cl : normal high ? cl : normal low cautions : 1. since the do pin is an n-channel op en-drain output, the transition times (t dc , t dh ) will differ with the value of the pull-up resistor used. 2. the ce, cl, di, and do pins can be connected to the co rresponding pins on other ics th at use the ccb interface. (however, we recommend connecting the do and ce pins se parately if the number of available microcontroller ports allows it.) 3. serial data i/o becomes possible after the crystal oscillator starts oscillation. t su t hd t el t es t eh t lc t ce b0 b1 b2 b3 a0 a1 a2 a3 fs0 ct1 fs1 0 fs2 sp0 fs3 sp1 ec3 ts0 ec4 ts1 ct0 ts2 0 ts3 ce cl di internal data t su t hd t el t es t eh t dc t dc t ce b0 b1 b2 b3 a0 a1 a2 a3 1 0 1 0 d3 d2 d1 d0 ce cl di do t dh t su t hd t el t es t eh t lc t ce b0 b1 b2 b3 a0 a1 a2 a3 fs1 0 fs0 ct1 fs2 sp0 fs3 sp1 ec3 ts0 ec4 ts1 ct0 ts2 0 ts3 ce cl di t su t hd t dc t dc b0 b1 b2 b3 a0 a1 a2 a3 1 0 1 0 d3 d2 d1 d0 ce cl di do t dh t el t es t eh t ce internal data
lc72722pm www.onsemi.com 16 (3) serial data timing ? cl : normal high ? cl : normal low parameter symbol cond itions min typ max unit data setup time t su di, cl 0.75 ? s data hold time t hd di, cl 0.75 ? s clock low level time t cl cl 0.75 ? s clock high level time t ch cl 0.75 ? s ce wait time t el ce, cl 0.75 ? s ce setup time t es ce, cl 0.75 ? s ce hold time t eh ce, cl 0.75 ? s ce high level time t ce ce 20 ms data latch transition time t lc 1.15 ? s data output time t dc do, cl differs with the value of the pull-up resistor used. 0.46 ? s t dh do, ce 0.46 ? s t ce v ih v il v il v ih v il t eh t dh t lc t es t dc t dc t el old old new new t cl t ch t su t hd v ih v il v ih v il v ih v il v il ce cl di do t ce v ih v il v ih v il t eh t dh t lc t es t dc t el t cl t ch t su t hd v ih v il v ih v il v ih v il v ih ce cl di do internal data latch internal data latch
lc72722pm www.onsemi.com 17 do pin operation this ic incorporates a ram data buffer that can hold up to 24 blocks of data. at the point when one block of data is written to this ram, the ic issues a read reque st by switching the do pin from high to low. the do pin always goes high for a fixed period (tdo = 265 ? s) after a readout and ce goes low. when all the data in the data buffer has been read out, the do pin is held in th e high state until a new block of data has been written to the ram. if there is data that has not yet been read remaining in the data buffer, the do pin goes low after the tdo time has elapsed. after a synchronization reset, the do pin is held high until sync hronization is established. it goes low at the point the ic synchronizes. ? when the do pin is high following the 265 ? s period (tdo) after data is read out. here, the buffer is in the empty state, i.e. the state wher e new data has not been written. after this, when the do pin goes low, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 480 ms of do going low. ? when do goes low 265 ? s after data is read out here, there is data that has not been read out remaining in the data buffer. in this case, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 20 ms of do going low. (note that this is the worst case condition.) notes : 1. although an application can determine whether or not there is data remaining in the buffer by checking the do level with the above timing, checking the re and rf flags in the serial data is a preferable method. 2. applications are not limited to reading out one block of data at a time, but rather can read out multiple blocks of data continuously as described above. when usi ng this method, if an application referen ces the re and rf flags in the data while reading out data, it can determine the amount of data remaining. howeve r, the length of the period for data readout (the period the ce pin remains high) must be kept under 20 ms. 3. if the do pin is shared with other ics that use the ccb in terface, the application must identify which ic issued the readout request. one method is to read out data from the lc72722pm and either check whether meaningful data has been read (if the lc72722pm is not requestin g a read, data consisting of all zeros w ill be read out) or check whether the do level goes low within the 256 ? s following the completion of the read (if the do pin goes low, then the request was from another ic). ce pin do pin (last data)-1 last data new data t tdo do check (tdo < t) ce pin do pin (last data)-2 (last data)-1 last data t tdo do check (tdo < t)
lc72722pm www.onsemi.com 18 on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and othe r intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety require ments or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life sup port systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended fo r implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer sh all indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, d amages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resal e in any manner. sample application circuit caution : 1. determine the value of the do pin pull-up resist or based on the required serial data transfer speed. 2. if the syr pin is unused, it must be connected to ground. ordering information device package shipping (qty / packing) lc72722pm-mpb-e soic24 w / mfp24 (375mil) (pb-free) 25 / fan-fold LC72722PM-TLM-E soic24 w / mfp24 (375mil) (pb-free) 1000 / tape & reel ? for information on tape and reel specifications, including part orientation and tape sizes, plea se refer to our tape and reel packaging specifications brochure, brd8011/d. h ttp://www.onsemi.com/pub_lin k/collateral/brd8011-d.pdf + 124 v ref syr syr 223 mpxin ce 322 vdda di 421 vssa cl 520 flout do 619 cin rds-id 718 t1 sync 12 13 x out x in 10 f mpxin vdda vssa 8 t2 vssd 9 t3 nc nc nc nc nc 10 t4 11 t5 vssd vssd 330 pf 560 pf 22 pf 22 pf 17 t7 16 t6 vssd vssd vddd 0.1 f 15 vssd 14 vddd 0.1 f vssa 4.332 mhz di ce cl do vddd 10 k vddd 10 k rds-id sync vddd 10 k

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